1. Technical Field
The present invention relates to an output buffer circuit, and more particularly, to an output buffer circuit having a signal path used for testing and a test method of the same.
2. Description
In general, before shipping goods related to a semiconductor device, a performance test is implemented on the semiconductor device to check whether or not defects have occurred during the manufacturing process. A procedure of evaluating the characteristic of output buffers is included in the performance test of the semiconductor device. During the procedure of evaluating the characteristics of the output buffers, it is checked whether or not the output signals VOH or VOL, which are output from the output buffers, have voltage levels within a predetermined range. Here, the output signals VOH have a “high” voltage level, and the output signals VOL have a “low” voltage level.
Meantime, the voltage level ranges of the output signals VOH or VOL are determined by the current drive capability of the output buffers of the semiconductor device. In further detail, even though two output buffers output signals VOH having a “high” voltage level, the voltage levels are different between signals VOH output from an output buffer having a current drive capability of 2 mA and signals VOH output from an output buffer having a current drive capability of 1 mA. Thus, the output buffers of the semiconductor device output signals VOH or VOL having different voltage levels depending on their current drive capability.
In the conventional art, automatic test equipment (ATE) has been used to evaluate the characteristics of output buffers of a semiconductor device. One example of ATE is disclosed in U.S. Pat. No. 6,286,120. An explanation of the ATE disclosed in U.S. Pat. No. 6,286,120 will be made below with reference to FIG. 1.
FIG. 1 is a block diagram of a semiconductor device having an output buffer circuit and ATE according to the conventional art.
Referring to FIG. 1, the semiconductor device 200 to be tested is connected to the ATE 100. The ATE 100 is controlled by a control computer 300. The control computer 300 includes a high capacity memory device, such as a disk 310, and executes a program called “pattern”. The pattern includes information on stimulus signals, which are applied to the semiconductor device 200, an order in which the signals are applied, and expected responses from the semiconductor device 200. Here, the above information, with respect to any test cycle of the ATE 100, is called a vector.
The ATE 100 includes a pattern generator 110, a formatter 120, and a failure processor 130. The pattern generator 110 includes a pattern generator control circuit 111, a pattern data memory 112, and a pattern control memory 113. The pattern data memory 112 outputs to the formatter 120 data bits corresponding to an address received from the pattern generator control circuit 111. Vectors stored in the pattern data memory 112 include data bits, and vectors stored in the pattern control memory 113 include control bits.
The ATE 100 constructed in the manner described above is controlled by the control computer 300 for testing the semiconductor device 200. The pattern generator control circuit 111 generates a predetermined address signal under the control of the control computer 300. The pattern data memory 112 outputs data bits corresponding to the address signal to the formatter 120, and the formatter 120 applies the data bits to the semiconductor device 200 through a plurality of signal lines.
Here, referring to FIG. 2, the semiconductor device 200 receives the data bits through an input buffer circuit 210. The received data bits are transmitted to an output buffer circuit 230 through an internal logic circuit 220. The output buffer circuit 230 outputs response signals as data bits. The input buffer circuit 210 includes a plurality of input buffers 211, and the output buffer circuit 230 includes a plurality of output buffers 231.
Referring to FIG. 1 again, the formatter 120 receives the response signals output from the output buffer circuit 230 of the semiconductor device 200. The formatter 120 compares the response signals with data stored in the pattern data memory 112, and outputs comparison results to the failure processor 130. If the comparison results indicate that the response signals are not identical to the data stored in the pattern data memory, the failure processor 130 recognizes that an error exists, and transmits failure information corresponding to the error to the control computer 300.
In this manner, the characteristic of the output buffers is evaluated by the ATE.
In the evaluation of the characteristic of the output buffers, which uses the ATE, the vectors, including the data bits applied to the semiconductor device, are delayed while passing through the input buffers and the internal logic circuit. As a result, even though vectors for generating output signals VOL, which have a “low” voltage level, are inputted to the input buffers after vectors for generating output signals VOH, which have a “high” voltage level, the output buffers output signals VOH that have the previous voltage level. Therefore, the internal logic circuit in the semiconductor device affects the timing margin between output signals VOH or VOL.
Thus, the ATE applies vectors for generating output signals VOH of the output buffers to the input buffers, and then checks whether or not voltage levels of the output signals are within a predetermined range while stopping the application of vectors for generating next output signals VOL. Next, the ATE applies vectors for generating the output signals VOL of the output buffers to the input buffers, and then checks whether or not voltage levels of the output signals VOL are within a predetermined range while stopping the application of next vectors.
Furthermore, when evaluating the characteristic of the output buffers by using the ATE, the internal logic circuit in the semiconductor device affects the voltage levels of the output signals VOH or VOL of the output buffers. In further detail, for example, a case exists where an output buffer, with a condition that indicates the voltage level of an output signal VOH having a “high” voltage level should exceed 0.8V, outputs an output signal VOH having a voltage level of 0.804V or 0.805V. Due to a level decrease caused by the internal logic circuit this voltage level just satisfies the above condition. In this case, it is difficult to exactly evaluate the characteristic of the output buffer. On the other hand, semiconductor devices operating at a low voltage level, such as 1.2V, 1.0V, or 0.7V are now being developed, and the level decrease of output signals caused by the internal logic circuit becomes a serious problem in the evaluation of the characteristic of the output buffers.
As described above, since the influence of the internal logic circuit cannot be avoided during an evaluation of the characteristic of the output buffers which uses the ATE, there is an urgent need for a new test method that more precisely evaluates and analyzes the output buffers.
Accordingly, it would be desirable to provide an output buffer circuit having a signal path used for testing which can exactly evaluate the characteristic of output buffers without being affected by an internal logic circuit. It would also be desirable to provide a test method that can exactly evaluate the characteristic of output buffers without being affected by an internal logic circuit.
According to one aspect of the present invention, an output buffer circuit for outputting output signals at set logic levels in response to internal output signals received from an internal logic circuit, the output buffer circuit comprising: a first control input adapted to receive a control signal; a second control input adapted to receive a test signal having a set voltage; a test signal input circuit adapted to switch between a test mode and a normal mode in response to the control signal, to receive and output the test signal while in the test mode, and to receive and output the internal output signals while in the normal mode; and a plurality of output buffers adapted to output the output signals from the output buffer circuit through a plurality of outputs in response to one of the internal output signals and the test signal, which are output from the test signal input circuit.
According to another aspect of the present invention, a method of testing an output buffer circuit having a signal path used for testing, wherein the output buffer circuit includes a first control input, which receives a control signal; a second control input, which receives a test signal; a test signal input circuit, which switches between a test mode and a normal mode in response to the control signal, receives and outputs the test signal while in the test mode, and receives and outputs internal output signals output from an internal logic circuit while in the normal mode; and a plurality of output buffers for outputting output signals at set logic levels through a plurality of outputs in response to one of the test signal and the internal output signals, comprises: (a) connecting a control circuit, which generates the control signal and the test signal, to the first control input and the second control input, and connecting an output voltage measuring circuit to the plurality of outputs; (b) enabling the control signal, which is inputted through the first control input from the control circuit, for the purpose of switching to the test mode; (c) generating a first test signal using the control circuit and inputting the first test signal through the second control input; (d) measuring the voltage of the first output signal, among the output signals output from the plurality of outputs, using the output voltage measuring circuit; (e) generating a second test signal using the control circuit and inputting the second test signal through the second control input; and (f) measuring the voltage of the second output signal, among the output signals output from the plurality of outputs, using the output voltage measuring circuit.
According to another aspect of the present invention, an integrated circuit device, comprises an internal logic circuit adapted to provide a plurality of internal output signals; a first control input adapted to receive a control signal; a second control input adapted to receive a test signal; and an output buffer circuit, comprising: a test signal input circuit adapted to switch between a test mode and a normal mode in response to the control signal, to receive and output the test signal while in the test mode, and to receive and output the internal output signals while in the normal mode; and a plurality of output buffers, each adapted to receive and output the test signal from the test signal input circuit while in the test mode, and to receive and output a corresponding one of the internal output signals from the test signal input circuit while in the normal mode.